The present invention relates to the field of programmable devices, and the systems and methods for programming the same. Programmable devices, such as FPGAs, typically includes thousands of programmable logic cells that use combinations of logic gates and/or look-up tables to perform a logic operation. Programmable devices also include a number of functional blocks having specialized logic devices adapted to specific logic operations, such as adders, multiply and accumulate circuits, phase-locked loops, and one or more embedded memory array blocks. The logic cells and functional blocks are interconnected with a configurable switching circuit. The configurable switching circuit selectively routes connections between the logic cells and functional blocks. By configuring the combination of logic cells, functional blocks, and the switching circuit, a programmable device can be adapted to perform virtually any type of information processing function.
The process of determining the configuration of a programmable device from a user-specified design is referred to as compilation. Typical compilation processes start with an extraction phase, followed by a logic synthesis phase, a clustering and placement phase, a routing phase, and an assembly phase. The extraction phase takes a user design, typically expressed as a netlist in a hardware description language such as Verilog or VHDL, and produces a set of logic gates implementing the user design. In the logic synthesis phase, the set of logic gates is permuted over the hardware architecture of the programmable device in order to match elements of the user design with corresponding portions of the programmable device.
The clustering phase partitions the design into subsets of components capable of being implemented by the logic cells and other of components of the programmable device. The placement phase assigns the subsets of components to specific logic blocks and other components of the programmable device. The routing phase determines the configuration of the configurable switching circuit used to route signals between these logic blocks and functional blocks, taking care to satisfy the user timing constraints as much as possible. In the assembly phase, a configuration file defining the programmable device configuration implementing the user design is created. The programmable device configuration can then be loaded into a programmable device to implement the user design. Programmable devices can be configured with the a user design during or after manufacturing.
The timing or propagation delay of signals through an electronic circuit is an important metric of circuit performance. Compilation software typically optimizes the configuration of a user design to minimize timing delays on critical signal paths, allowing the programmable device implementing the user design to operate as fast as possible. Users may provide design constraints, such as timing, power, area, and other constraints, which the compilation software will attempt to satisfy.
Optimizations in the logic synthesis, clustering, placement, and routing phases can determine whether a configuration of a design satisfies its design constraints and possibly make modifications to the configuration to achieve those constraints, for example by placing the elements of longer or critical paths more closely together, using alternative routing resources or by modifying the mapping of the logical functionality of the design to different gates. To optimize user designs, compilation software typically estimates the timing delays and other characteristics of potential configurations of the user design. Previous compilation software estimates timing delays of circuit signal paths as constant values.
However, the timing delays of signal paths in actual devices are not generally constant values. Timing delay values vary with the environment, such as temperature and voltage conditions, and on random manufacturing process fluctuations in the fabrication of the device. The variations in timing delays of signal paths, as well as other attributes such as power consumption, may be global, affecting all of the elements of a device, wafer, or lot uniformly; regional or spatial, affecting elements of a device in physical proximity equally; and/or randomized and local, affecting only a single element, such as a wire or transistor.
Prior compilation software can account for variability in devices using guard bands. Each element is assigned a single worst case attribute value for the purpose of computing longest-path (setup) criticality. For example, if the timing delay of a wire has a mean of 50 ps and a standard deviation (sigma) of 10 ps, the worst case timing delay of the wire may be set to 70 ps, which is two standard deviations from the mean and includes approximately 95% of the possible timing delays of the wire. This worst case guard band timing delay value can be used to optimize the design. However, this guard band is too conservative for long signal paths including many wires, because the probability of having a total timing delay outside of the timing limits is statistically negligible (e.g. 0.0520 is approximately 0). Conversely, this guard band is too aggressive for short signal paths with relatively few wires. Even if the probability of the total timing delay of a signal path is relatively small, such as 0.01%, a design will typically have millions of wires, which virtually guarantees that at least one short signal path in a design will have a total timing delay outside the guard band. In a similar manner, timing analysis may use a single best-case attribute value, e.g. on clock paths, for the shortest path delay for the purpose of computing hold-time violations.
Prior compilation software using guard bands typically concentrate their optimizations on a single timing-critical signal path. However, this ignores many near critical signal paths, which due to variances may become critical themselves.
It is therefore desirable for compilation techniques to better account for variations of device attributes in optimizing designs. It is further desirable for compilation techniques to provide improved yields for devices. It is also desirable for compilation techniques to provide yield estimates to designers for different speed grades of devices.